1. Field of the Invention
The present invention pertains generally to the field of radio frequency (RF) power transistor devices and, more specifically, to methods and apparatus for assembling RF power packages for wireless communication applications.
2. Background
The use of RF power transistor devices as signal amplifiers in wireless communication applications is well known. With the considerable recent growth in the demand for wireless services, such as personal communication services, the operating frequency of wireless networks has increased dramatically and is now well into the gigahertz frequencies. At such high frequencies, laterally diffused, metal oxide semiconductor (LDMOS) transistors have been preferred for RF power amplification applications, e.g., for use in antenna base stations.
Referring to FIGS. 1-2, an exemplary LDMOS power transistor package (or xe2x80x9cpower packagexe2x80x9d) 18 generally comprises a plurality of transistor elements connected to form respective electrodes 20 on a semiconductor die 22. The electrodes 20 are coupled to a common input (gate) terminal 24 and output (drain) terminal 26 formed on the top surface of the die 22. The electrodes 20 also share a common ground (source) terminal (not shown) formed on the underlying side of the die 22.
The die 22 is attached, e.g., by a known eutectic die attach process, to a top surface 28 of a conductive flange 30. In particular, the flange 30 serves as a combined ground current reference, heat spreader and mounting device for the power package 18, with the electrode ground terminal on the underside of the die 22 directly coupled to the flange surface 28.
A thermally conductive, but electrically isolating, e.g., aluminum oxide, xe2x80x9cwindowxe2x80x9d substrate 32 is attached to the mounting flange 30, surrounding the die 22. Respective input and output lead frames 34 and 36 are attached at opposing ends of a top surface 38 of the window substrate 32, electrically isolated from the flange 30. An input matching capacitor 40 comprising a silicon wafer with a gold alloy top-side terminal 41, is attached to the flange surface 28 between the input lead frame 34 and the die 22. A similarly constructed output matching capacitor 42 having a gold-alloy top-side terminal 43 is attached to the flange surface 28 between the die 22 and the output lead frame 36. The respective input and output matching capacitors 40 and 42 are typically attached to the flange surface 28 as part of the same eutectic scrubbing process used to attach the die 22.
In the input direction, a first plurality of wires 44 couple the input lead frame 34 to the input matching capacitor terminal 41, and a second plurality of wires 46 couple the input matching capacitor terminal 41 to the electrode input terminals 24. In the output direction, a third plurality of wires 48 couple the electrode output terminals 26 to the output blocking capacitor terminal 43, and a fourth plurality of wires couple the output blocking capacitor terminal 43 to the output lead frame 36.
As part of a large scale assembly of such LDMOS power packages, it is highly desirable to be able to attach the die and matching capacitors in the same relative locations on each mounting flange surface. While this may be readily accomplished using precise robotic die attach machines, such machines are relatively expensive and slow. The die attachment process may alternately be done manually, which is relatively fast and inexpensive. However, a manual attachment process requires use of a microscope with reticules for precisely measuring the desired distances, which can result in inconsistent results, since the reticules require re-calibration from operator to operator.
If the die or capacitors are placed on the flange surface inconsistently, the wire bond operator must change the wiring program (e.g., lengths and bond locations) to accommodate for the misplaced die or capacitor elements. Importantly, at such high operating frequencies, even small changes in bond wire lengths can significantly alter the performance of the power package, due to the corresponding changes in inductance through the transmission signal path.
Thus, it would be desirable to provide a relatively fast and inexpensive means for positioning the die and capacitor elements on the flange surface as part of the LDMOS power package assembly process.
An LDMOS power package includes a mounting substrate having a surface with one or more alignment pedestals extending therefrom. Each alignment pedestal has a mounting surface facing away from the substrate surface to provide for uniform positioning of various semiconductor elements, e.g., a transistor die or matching capacitors, relative to the substrate surface as part of a large scale production process. The respective pedestal mounting surfaces are preferably conductive, and are electrically coupled to the flange surface, so as to electrically couple the respective capacitor and electrode ground terminals to the flange.
As will be apparent to those skilled in the art, other and further aspects and advantages of the present invention will appear hereinafter.